Hybrid Semiconductor/Nanoelectronic Circuits

This is a very brief review of the recent work on the development of hybrid semiconductor/nanodevice integrated circuits. Such a circuit will combine a CMOS subsystem, and a nanowire crossbar with simple bistable two-terminal devices formed at each crosspoint, connected with an area-distributed “CMOL” interface. Simulations have shown that the hybrid circuits may serve as the basis for (i) terabit-scale memories with access time below 100 ns and defect tolerance up to 10%, (ii) FPGA-like reconfigurable logic circuits with density at least two orders of magnitude higher than that of CMOS FPGAs, and (iii) mixed-signal neuromorphic networks (“CrossNets”) which may become the first hardware basis for challenging the human cerebral cortex in both areal density and speed. Recently the work on the hybrid CMOS/nano circuits received a strong boost from the experimental demonstration of reproducible metal-oxide devices and nanowire crossbars with 15-nm-scale half-pitch.